aimed at regaining that lead by 2025, the research work unveiled Saturday gives a look into how Intel plans to compete beyond 2025.One of the ways Intel is packing more computing power into chips by stacking up "tiles" or "chiplets" in three dimensions rather than making chips all as one two-dimension piece. Intel showed work Saturday that could allow for 10 times as many connections between stacked tiles, meaning that more complex tiles can be stacked on top of one another.
But perhaps the biggest advance showed Saturday was a research paper demonstrating a way to stack transistors - tiny switches that form the most basic building bocks of chips by representing the 1s and 0s of digital logic - on top of one another. Intel believes the technology will yield a 30% to 50% increase in the number of transistors it can pack into a given area on a chip. Raising the number of transistors is the main reason chips have consistently gotten faster over the past 50 years.
"By stacking the devices directly on top of each other, we're clearly saving area," Paul Fischer, director and senior principal engineer of Intel's Components Research Group told Reuters in an interview. "We're reducing interconnect lengths and really saving energy, making this not only more cost efficient, but also better performing.
They aren’t doing themselves any favors by disproving this research with their last decade of subpar processors.